Building a 1-Bit Oversampling SDR with not much more than a low cost FPGA

Thank you to Alberto Garlassi for submitting information about his super low parts home made FPGA software defined radio which is capable of medium wave and shortwave AM reception. What makes this design interesting is that is is created with nothing more than 3 resistors, 1 capacitor, and a low cost 30€ Lattice MachXO2 FPGA dev board.

The design makes use of the FPGA's LVDS buffer input to implement a direct sampling 1-bit ADC to which a wire antenna is directly connected to. This 1-bit resolution is increased by using an SDR trick that involves superimposing random RF noise onto the desired signal, and oversampling at 80 MHz then decimating down to a 6 kHz bandwidth. This results in an effective ADC resolution of 6-bits, from 1-bit hardware.

Synthesized on the FPGA is the ADC, Mixer, two CIC filters, an AM demodulator and a PWM circuit for audio output. The synthesis allows for medium wave and shortwave AM reception where the frequency can be tuned via PC control.

The FPGA Verilog synthesis files are available on the projects' GitHub page, and a more in depth explanation of the SDRs operation is available on its hackaday.io page. Alberto has also created a short demonstration video which is shown below.

FPGA + 3 R + 1 C = Medium and Long Wave SDR Receiver.

One comment

  1. Max

    All the experimenting is important, regardless the results or practical use, and allow to learn concepts that can be used for future work.
    For practical use we have to consider that a MSI.SDR is less than $40.

Post a comment

You may use the following HTML:
<a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <s> <strike> <strong>

This site uses Akismet to reduce spam. Learn how your comment data is processed.