FPGAs for DSP and Software-Defined Radio: Short Course at UCLA

The University of California, Los Angeles is hosting a 3-day hands on short course on using SDR’s like the RTL-SDR with FPGA hardware and MATLAB Simulink. This is a course with a high knowledge pre-requisite, so you will likely need qualifications and/or knowledge equivalent to a bachelors in Electrical/Computer Engineering to be able to understand the material. It is mainly intended for DSP and Communications Engineers, HDL designers, FPGAs engineers, RF engineers, and systems engineers. The course runs for 3 days between 10 – 12 October. The main blurb of the course is described below:

One of the main aims of this course is to demonstrate the workflow required to take floating point Simulink receivers (such as the ones presented in the book) and target them onto SDR hardware. This means converting to fixed point, generating HDL code, and then packaging it into something that can be deployed to ZynqSDR hardware.

In this short course we will present, review, simulate then implement real-time DSP enabled software defined radios (SDR) on laptops, Raspberry Pis, Xilinx (Zynq) SoC FPGAs with RF transceivers. The design, simulation and implementation will take the form of a complete model based design work-flow from within MathWork’s MATLAB and Simulink software tools. The course will ensure attendees are educated in key relevant multi-rate DSP algorithms and techniques, in communications modulation methods, quadrature/QAM transceiver designs, and timing and synchronisation. The first part of the course will educate on DSP and communications, followed by a second part on FPGA systems implementation (focussing on Xilinx Zynq SoC) and introduce MathWorks Embedded and HDL Coder methods for hardware targeting. In the third and final part of the course we will develop real-time ‘desktop’ implementations of SDR transceivers using a model based design flow. We will start with floating point designs, which will evolve to fixed point, and then undergo final code generation stages with the Embedded and HDL Coder packages prior to FPGA deployment..

All attendees on the course will use (and take home!) an RTL-SDR device (which tunes from 25MHz to 1.75GHz) and have access to a Raspberry Pi and Zynq SDR kits in class hosting the RTL-SDR device and a wideband FMComms RF card respectively. The class format will be 40% lecture, 20% live SDR demonstration and 40% hands-on ‘desptop SDR’ using software and SDR hardware. 

This course is related to the desktopsdr.com text book which was released September 2015. The physical copy of the book can be purchased on Amazon, or downloaded for free in pdf form on their desktopsdr.com website.